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1/21 june 2001 m95256 m95128 256/128 kbit serial spi bus eeprom with high speed clock n spi bus compatible serial interface n supports positive clock spi modes n 5 mhz clock rate (maximum) n single supply voltage: C 4.5v to 5.5v for m95xxx C 2.7v to 3.6v for m95xxx-v C 2.5v to 5.5v for m95xxx-w C 1.8v to 3.6v for m95xxx-s n status register n hardware protection of the status register n byte and page write (up to 64 bytes) n self-timed programming cycle n resizeable read-only eeprom area n enhanced esd protection n more than 100,000 erase/write cycles n more than 40 year data retention description these spi-compatible electrically erasable programmable memory (eeprom) devices are organized as 32k x 8 bits (m95256) and 16k x 8 bits (m95128), and operate down to 2.7 v (for the -v version), 2.5 v (for the -w version), and down to 1.8 v (for the -s version of each device). figure 1. logic diagram ai01789c s v cc m95xxx hold v ss w q c d table 1. signal names c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground pdip8 (bn) 0.25 mm frame so8 (mn) 150 mil width tssop14 (dl) 169 mil width 8 1 8 1 so8 (mw) 200 mil width 8 1
m95256, m95128 2/21 the m95256 and m95128 are available in plastic dual-in-line, plastic small outline and thin shrink small outline packages. each memory device is accessed by a simple serial interface that is spi bus compatible. the bus signals are c, d and q, as shown in table 1 and figure 3. the device is selected when the chip select input (s ) is held low. communications with the chip can be interrupted using the hold input (hold ). figure 2a. dip connections figure 2b. so connections d v ss c hold q sv cc w ai01790c m95xxx 1 2 3 4 8 7 6 5 1 ai01791c 2 3 4 8 7 6 5 d v ss c hold q sv cc w m95xxx figure 2c. tssop connections note: 1. nc = not connected 1 ai02346b 2 3 4 14 9 10 8 d v ss wc s hold m95xxx nc q nc nc nc nc nc 5 6 7 12 13 11 v cc table 2. absolute maximum ratings 1 note: 1. except for the rating operating temperature range, stresses above those listed in the table absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditio ns above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the st sure program and other relevant quality documents. 2. ipc/jedec j-std-020a 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 w , r2=500 w ) symbol parameter value unit t a ambient operating temperature C40 to 125 c t stg storage temperature C65 to 150 c t lead lead temperature during soldering pdip8: 10 seconds so8: 20 seconds (max) 2 tssop8: 20 seconds (max) 2 260 235 235 c v o output voltage range C0.3 to v cc +0.6 v v i input voltage range C0.3 to 6.5 v v cc supply voltage range C0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) 3 4000 v
3/21 m95256, m95128 signal description serial output (q) the output pin is used to transfer data serially out of the memory. data is shifted out on the falling edge of the serial clock. serial input (d) the input pin is used to transfer data serially into the device. instructions, addresses, and the data to be written, are each received this way. input is latched on the rising edge of the serial clock. serial clock (c) the serial clock provides the timing for the serial interface (as shown in figure 4). instructions, addresses, or data are latched, from the input pin, on the rising edge of the clock input. the output data on the q pin changes state after the falling edge of the clock input. chip select (s ) when s is high, the memory device is deselected, and the q output pin is held in its high impedance state. unless an internal write operation is underway, the memory device is placed in its stand-by power mode. after power-on, a high-to-low transition on s is required prior to the start of any operation. write protect (w ) the protection features of the memory device are summarized in table 3. the hardware write protection, controlled by the w pin, restricts write access to the status register (though not to the wip and wel bits, which are set or reset by the device internal logic). bit 7 of the status register (as shown in table 5) is the status register write disable bit (srwd). when this is set to 0 (its initial delivery state) it is possible to write to the status register if the wel bit (write enable latch) has been set by the wren instruction (irrespective of the level being applied to the w input). when bit 7 (srwd) of the status register is set to 1, the ability to write to the status register depends on the logic level being presented at pin w : Cif w pin is high, it is possible to write to the status register, after having set the wel bit using the wren instruction (write enable latch). Cif w pin is low, any attempt to modify the status register is ignored by the device, even if the wel bit has been set. as a consequence, all the data bytes in the eeprom area, protected by the bpn bits of the status register, are also hardware protected against data corruption, and appear as a read only eeprom area for the microcontroller. this mode is called the hardware protected mode (hpm). it is possible to enter the hardware protected mode (hpm) either by setting the srwd bit after pulling low the w pin, or by pulling low the w pin after setting the srwd bit. the only way to abort the hardware protected mode, once entered, is to pull high the w pin. if w pin is permanently tied to the high level, the hardware protected mode is never activated, and figure 3. microcontroller and memory devices on the spi bus ai03746c bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold
m95256, m95128 4/21 the memory device only allows the user to protect a part of the memory, using the bpn bits of the status register, in the software protected mode (spm). hold (hold ) the hold pin is used to pause the serial communications between the spi memory and controller, without losing bits that have already been decoded in the serial sequence. for a hold condition to occur, the memory device must already have been selected (s = 0). the hold condition starts when the hold pin is held low while the clock pin (c) is also low (as shown in figure 5). during the hold condition, the q output pin is held in its high impedance state, and the levels on the input pins (d and c) are ignored by the memory device. it is possible to deselect the device when it is still in the hold state, thereby resetting whatever transfer had been in progress. the memory remains in the hold state as long as the hold pin is low. to restart communication with the device, it is necessary both to remove the hold condition (by taking hold high) and to select the memory (by taking s low). operations all instructions, addresses and data are shifted serially in and out of the chip. the most significant bit is presented first, with the data input (d) sampled on the first rising edge of the clock (c) after the chip select (s ) goes low. every instruction starts with a single-byte code, as summarized in table 4. this code is entered via the data input (d), and latched on the rising edge of the clock input (c). to enter an instruction code, the product must have been previously selected (s held low). if an invalid instruction is sent (one not contained in table 4), the chip automatically deselects itself. write enable (wren) and write disable (wrdi) the write enable latch, inside the memory device, must be set prior to each write and wrsr operation. the wren instruction (write enable) sets this latch, and the wrdi instruction (write disable) resets it. the latch becomes reset by any of the following events: C power on C wrdi instruction completion C wrsr instruction completion C write instruction completion. table 3. write protection control on the m95256 and m95128 w srwd bit mode status register data bytes protected area unprotected area 0 or 1 0 software protected (spm) writeable (if the wren instruction has set the wel bit) software write protected by the bpn of the status register writeable (if the wren instruction has set the wel bit) 11 01 hardware protected (hpm) hardware write protected hardware write protected by the bpn bits of the status register writeable (if the wren instruction has set the wel bit) figure 4. data and clock timing ai01438 c c msb lsb cpha d or q 0 1 cpol 0 1
5/21 m95256, m95128 figure 5. hold condition activation figure 6. block diagram note: 1. the cell an represents the byte at the highest address in the memory ai02029b hold pin clock active memory status hold active hold active ai02030b hold s w control logic high voltage generator i/o shift register address register and counter data register 64 bytes x decoder y decoder size of the read only area of the eeprom c d q status register an an - 63 003fh 0000h
m95256, m95128 6/21 as soon as the wren or wrdi instruction is received, the memory device first executes the instruction, then enters a wait mode until the device is deselected. read status register (rdsr) the rdsr instruction allows the status register to be read, and can be sent at any time, even during a write operation. indeed, when a write is in progress, it is recommended that the value of the write-in-progress (wip) bit be checked. the value in the wip bit (whose position in the status register is shown in table 5) can be continuously polled, before sending a new write instruction, using the timing shown in figure 7. the write-in- process (wip) bit is read-only, and indicates whether the memory is busy with a write operation. a 1 indicates that a write is in progress, and a 0 that no write is in progress. the write enable latch (wel) bit indicates the status of the write enable latch. it, too, is read-only. its value can only be changed by one of the events listed in the previous paragraph, or as a result of executing wren or wrdi instruction. it cannot be changed using a wrsr instruction. a 1 indicates that the latch is set (the forthcoming write instruction will be executed), and a 0 that it is reset (and any forthcoming write instructions will be ignored). the block protect (bp0 and bp1) bits indicate the amount of the memory that is to be write- protected. these two bits are non-volatile. they are set using a wrsr instruction. during a write operation (whether it be to the memory area or to the status register), all bits of the status register remain valid, and can be read using the rdsr instruction. however, during a write operation, the values of the non-volatile bits (srwd, bp0, bp1) become frozen at a constant value. the updated value of these bits becomes available when a new rdsr instruction is executed, after completion of the write cycle. on the other hand, the two read-only bits (wel, wip) are dynamically updated during internal write cycles. using this facility, it is possible to poll the wip bit to detect the end of the internal write cycle. write status register (wrsr) the format of the wrsr instruction is shown in figure 8. after the instruction and the eight bits of the status register have been latched-in, the internal write cycle is triggered by the rising edge of the s line. this must occur before the rising edge of the 17 th clock pulse (as indicated in figure 14), otherwise the internal write sequence is not performed. the wrsr instruction is used for the following: n to select the size of memory area that is to be write-protected n to select between spm (software protected mode) and hpm (hardware protected mode). figure 7. read status register (rdsr) sequence c d s 2 1 3456789101112131415 instruction 0 ai02031c q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7 table 4. instruction set table 5. status register format note: 1. srwd, bp0 and bp1 are read and write bits. 2. wel and wip are read only bits. instruc tion description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read data from memory array 0000 0011 write write data to memory array 0000 0010 b7 b0 srwd x x x bp1 bp0 wel wip
7/21 m95256, m95128 the size of the write-protection area applies equally in spm and hpm. the bp1 and bp0 bits of the status register have the appropriate value (see table 6) written into them after the contents of the protected area of the eeprom have been written. the initial delivery state of the bp1 and bp0 bits is 00, indicating a write-protection size of 0. software protected mode (spm) the act of writing a non-zero value to the bp1 and bp0 bits causes the software protected mode (spm) to be started. all attempts to write a byte or page in the protected area are ignored, even if the write enable latch is set. however, writing is still allowed in the unprotected area of the memory array and to the srwd, bp1 and bp0 bits of the status register, provided that the wel bit is first set. hardware protected mode (hpm) the hardware protected mode (hpm) offers a higher level of protection, and can be selected by setting the srwd bit after pulling down the w pin or by pulling down the w pin after setting the srwd bit. the srwd is set by the wrsr instruction, provided that the wel bit is first set. the setting of the srwd bit can be made independently of, or at the same time as, writing a new value to the bp1 and bp0 bits. once the device is in the hardware protected mode, the data bytes in the protected area of the memory array, and the content of the status register, are write-protected. the only way to re- enable writing new values to the status register is to pull the w pin high. this cause the device to leave the hardware protected mode, and to revert to being in the software protected mode. (the value in the bp1 and bp0 bits will not have been changed). further details of the operation of the write protect pin (w ) is given earlier, on page 3. typical use of hpm and spm the w pin can be dynamically driven by an output port of a microcontroller. it is also possible, though, to connect it permanently to v ss (by a solder connection, or through a pull-down resistor). the manufacturer of such a printed circuit board can take the memory device, still in its initial delivery state, and can solder it directly on to the board. after power on, the microcontroller can be instructed to write the protected data into the table 6. write protected block size status register bits protected block array addresses protected bp1 bp0 m95256 m95128 0 0 none none none 0 1 upper quarter 6000h - 7fffh 3000h - 3fffh 1 0 upper half 4000h - 7fffh 2000h - 3fffh 1 1 whole memory 0000h - 7fffh 0000h - 3fffh figure 8. write status register (wrsr) sequence c d ai02282c s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
m95256, m95128 8/21 appropriate area of the memory. when it has finished, the appropriate values are written to the bp1, bp0 and srwd bits, thereby putting the device in the hardware protected mode. an alternative method is to write the protected data, and to set the bp1, bp0 and srwd bits, before soldering the memory device to the board. again, this results in the memory device being placed in its hardware protected mode. if the w pin has been connected to v ss by a pull- down resistor, the memory device can be taken out of the hardware protected mode by driving the w pin high, to override the pull-down resistor. if the w pin has been directly soldered to v ss , there is only one way of taking the memory device out of the hardware protected mode: the memory device must be de-soldered from the board, and connected to external equipment in which the w pin is allowed to be taken high. read operation the chip is first selected by holding s low. the serial one byte read instruction is followed by a two byte address (a15-a0), each bit being latched-in during the rising edge of the clock (c). the data stored in the memory, at the selected address, is shifted out on the q output pin. each bit is shifted out during the falling edge of the clock (c) as shown in figure 9. the internal address counter is automatically incremented to the next higher address after each byte of data has been shifted out. the data stored in the memory, at the figure 9. read data from memory array (read) sequence note: 1. depending on the memory size, as shown in table 7, the most significant address bits are dont care. c d ai01793c s q 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 765432 0 1 high impedance data out instruction 16 bit address 0 msb table 7. address range bits note: 1. b15 is dont care on the m95256 series. b15 and b14 are dont care on the m95128 series. device m95256 m95128 address bits a14-a0 a13-a0 figure 10. write enable (wren) sequence c d ai02281d s q 2 1 34567 high impedance 0 instruction
9/21 m95256, m95128 a write cycle, it is rejected, and the memory device deselects itself. byte write operation before any write can take place, the wel bit must be set, using the wren instruction. the write state is entered by selecting the chip, issuing three next address, can be read by successive clock pulses. when the highest address is reached, the address counter rolls over to 0000h, allowing the read cycle to be continued indefinitely. the read operation is terminated by deselecting the chip. the chip can be deselected at any time during data output. if a read instruction is received during figure 11. byte write data to memory array (write) sequence note: 1. depending on the memory size, as shown in table 7, the most significant address bits are dont care. c d ai01795c s q 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 high impedance instruction 16 bit address 0 765432 0 1 data byte 31 figure 12. page write data to memory array (write) sequence note: 1. depending on the memory size, as shown in table 7, the most significant address bits are dont care. c d ai01796c s 34 33 35 36 37 38 39 40 41 42 44 45 46 47 32 c d s 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 instruction 16 bit address 0 765432 0 1 data byte 1 31 43 765432 0 1 data byte 2 765432 0 1 data byte 3 65432 0 1 data byte n
m95256, m95128 10/21 bytes of instruction and address, and one byte of data. chip select (s ) must remain low throughout the operation, as shown in figure 11. the product must be deselected after the eighth bit of the data byte has been latched in, otherwise the write process is cancelled. as soon as the memory device is deselected, the self-timed internal write cycle is initiated. while the write is in progress, the status register may be read to check the status of the srwd, bp1, bp0, wel and wip bits. in particular, wip contains a 1 during the self-timed write cycle, and a 0 when the cycle is complete, (at which point the write enable latch is also reset). page write operation a maximum of 64 bytes of data can be written during one write time, t w , provided that they are all to the same page (see figure 6). the page write operation is the same as the byte write operation, except that instead of deselecting the device after the first byte of data, up to 63 additional bytes can be shifted in (and then the device is deselected after the last byte). any address of the memory can be chosen as the first address to be written. if the address counter reaches the end of the page (an address of the form xxxx xx11 1111) and the clock continues, the counter rolls over to the first address of the same page (xxxx xx00 0000) and over-writes any previously written data. as before, the write cycle only starts if the s transition occurs just after the eighth bit of the last data byte has been received, as shown in figure 12. data protection and protocol safety to protect the data in the memory from inadvertent corruption, the memory device only responds to correctly formulated commands. the main security measures can be summarized as follows: C the wel bit is reset at power-up. Cs must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile write cycle (in the memory array or in the status register). C accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. C after execution of a wren, wrdi, or rdsr instruction, the chip enters a wait state, and waits to be deselected. C invalid s and hold transitions are ignored. power on state after power-on, the memory device is in the following state: C low power stand-by state C deselected (after power-on, a high-to-low transition is required on the s input before any operations can be started). C not in the hold condition C the wel bit is reset C the srwd, bp1 and bp0 bits of the status register are un-changed from the previous power-down (they are non-volatile bits). initial delivery state the device is delivered with the contents of the memory array set at all 1s (or ffh). the status register bits are initialized to 00h, as shown in table 8. table 8. initial status register format table 9. ac measurement conditions note: 1. output hi-z is defined as the point where data is no longer driven. b7 b0 0 000 0 0 0 0 input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc input and output timing reference voltages 0.3v cc to 0.7v cc output load c l = 100 pf table 10. input parameters 1 (t a = 25 c, f = 5 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min. max. unit c out output capacitance (q) 8 pf c in input capacitance (other pins) 6 pf figure 13. ac testing input output waveforms ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc
11/21 m95256, m95128 table 11. dc characteristics (t a = 0 to 70 c, C40 to 85 c or C40 to 125 c; v cc = 4.5 to 5.5 v) (t a = 0 to 70 c or C40 to 85 c; v cc = 2.7 to 3.6 v) (t a = 0 to 70 c or C40 to 85 c; v cc = 2.5 to 5.5 v) (t a = 0 to 70 c or C20 to 85 c; v cc = 1.8 to 3.6 v) note: 1. for all 5v range devices, the device meets the output requirements for both ttl and cmos standards. symbol parameter voltage range temp. range test condition min. max. unit i li input leakage current all all 2 a i lo output leakage current all all 2 a i cc supply current 4.5-5.5 6 c=0.1v cc /0.9. v cc at 5 mhz, v cc = 5 v, q = open 4ma 4.5-5.5 3 c=0.1v cc /0.9. v cc at 2 mhz, v cc = 5 v, q = open 4ma 2.7-3.6 6 c=0.1v cc /0.9. v cc at 5 mhz, v cc = 2.7 v, q = open 3ma 2.5-5.5 6 c=0.1v cc /0.9. v cc at 2 mhz, v cc = 2.5 v, q = open 2ma 1.8-3.6 5 c=0.1v cc /0.9. v cc at 1 mhz, v cc = 1.8 v, q = open 2ma i cc1 supply current (stand-by) 4.5-5.5 6 s = v cc , v in = v ss or v cc , v cc = 5 v 10 a 4.5-5.5 3 s = v cc , v in = v ss or v cc , v cc = 5 v 20 a 2.7-3.6 6 s = v cc , v in = v ss or v cc , v cc = 2.7 v 2a 2.5-5.5 6 s = v cc , v in = v ss or v cc , v cc = 2.5 v 2 a 1.8-3.6 5 s = v cc , v in = v ss or v cc , v cc = 1.8 v 1 a v il input low voltage all all C 0.3 0.3 v cc v v ih input high voltage all all 0.7 v cc v cc +1 v v ol 1 output low voltage 4.5-5.5 6 i ol = 2 ma, v cc = 5 v 0.4 v 4.5-5.5 3 i ol = 2 ma, v cc = 5 v 0.4 v 2.7-3.6 6 i ol = 1.5 ma, v cc = 2.7 v 0.4 v 2.5-5.5 6 i ol = 1.5 ma, v cc = 2.5 v 0.4 v 1.8-3.6 5 i ol = 0.15 ma, v cc = 1.8 v 0.3 v v oh 1 output high voltage 4.5-5.5 6 i oh = C2 ma, v cc = 5 v 0.8 v cc v 4.5-5.5 3 i oh = C2 ma, v cc = 5 v 0.8 v cc v 2.7-3.6 6 i oh = C0.4 ma, v cc = 2.7 v 0.8 v cc v 2.5-5.5 6 i oh = C0.4 ma, v cc = 2.5 v 0.8 v cc v 1.8-3.6 5 i oh = C0.1 ma, v cc = 1.8 v 0.8 v cc v
m95256, m95128 12/21 table 12a. ac characteristics note: 1. t ch + t cl 3 1 / f c . 2. value guaranteed by characterization, not 100% tested in production. symbol alt. parameter m95256 / m95128 unit v cc =4.5 to 5.5 v t a =0 to 70c or -40 to 85c v cc =4.5 to 5.5 v t a =-40 to 125c min max min max f c f sck clock frequency d.c. 5 d.c. 2 mhz t slch t css1 s active setup time 90 200 ns t shch t css2 s not active setup time 90 200 ns t shsl t cs s deselect time 100 200 ns t chsh t csh s active hold time 90 200 ns t chsl s not active hold time 90 200 ns t ch 1 t clh clock high time 90 200 ns t cl 1 t cll clock low time 90 200 ns t clch 2 t rc clock rise time 1 1 s t chcl 2 t fc clock fall time 1 1 s t dvch t dsu data in setup time 20 40 ns t chdx t dh data in hold time 30 50 ns t dldh 2 t ri data in rise time 1 1 s t dhdl 2 t fi data in fall time 1 1 s t hhch clock low hold time after hold not active 70 140 ns t hlch clock low hold time after hold active 40 90 ns t chhl clock high set-up time before hold active 60 120 ns t chhh clock high set-up time before hold not active 60 120 ns t shqz 2 t dis output disable time 100 250 ns t clqv t v clock low to output valid 60 150 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 50 100 ns t qhql 2 t fo output fall time 50 100 ns t hhqx 2 t lz hold high to output low-z 50 100 ns t hlqz 2 t hz hold low to output high-z 100 250 ns t w t wc write time 10 10 ms
13/21 m95256, m95128 table 12b. ac characteristics note: 1. t ch + t cl 3 1 / f c . 2. value guaranteed by characterization, not 100% tested in production. symbol alt. parameter m95256-v / m95128-v m95256-w / m95128-w m95256-s / m95128-s unit v cc = 2.7 to 3.6 v t a =0 to 70c or C40 to 85c v cc = 2.5 to 5.5 v t a =0 to 70c or C40 to 85c v cc = 1.8 to 3.6 v t a =0 to 70c or C20 to 85c min max min max min max f c f sck clock frequency d.c. 5 d.c. 2 d.c. 1 mhz t slch t css1 s active setup time 90 200 400 ns t shch t css2 s not active setup time 90 200 400 ns t shsl t cs s deselect time 100 200 300 ns t chsh t csh s active hold time 90 200 400 ns t chsl s not active hold time 90 200 400 ns t ch 1 t clh clock high time 90 200 400 ns t cl 1 t cll clock low time 90 200 400 ns t clch 2 t rc clock rise time 0.05 1 1 s t chcl 2 t fc clock fall time 0.05 1 1 s t dvch t dsu data in setup time 20 40 60 ns t chdx t dh data in hold time 30 50 100 ns t dldh 2 t ri data in rise time 0.05 1 1 s t dhdl 2 t fi data in fall time 0.05 1 1 s t hhch clock low hold time after hold not active 70 140 350 ns t hlch clock low hold time after hold active 40 90 200 ns t chhl clock high set-up time before hold active 60 120 250 ns t chhh clock high set-up time before hold not active 60 120 250 ns t shqz 2 t dis output disable time 100 250 500 ns t clqv t v clock low to output valid 60 150 380 ns t clqx t ho output hold time 0 0 0 ns t qlqh 2 t ro output rise time 50 100 200 ns t qhql 2 t fo output fall time 50 100 200 ns t hhqx 2 t lz hold high to output low-z 50 100 250 ns t hlqz 2 t hz hold low to output high-z 100 250 500 ns t w t wc write time 10 10 10 ms
m95256, m95128 14/21 figure 14. serial input timing figure 15. hold timing figure 16. output timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c q ai02032 s d hold tchhl thlch thhch tchhh thhqx thlqz c q ai01449c s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv
15/21 m95256, m95128 table 13. ordering information scheme note: 1. produced with high reliability certified flow (hrcf), in v cc range 4.5 v to 5.5 v only. 2. the -s version (v cc range 1.8 v to 3.6 v) only available in temperature ranges 5 or 1. 3. so8, 150 mil width, package is available for the m95128 series only. 4. tssop14, 169 mil width, package is available for the m95128 series only. example: m95256 Cw mw 6 t memory capacity option 256 256 kbit (32k x 8) t tape and reel packing 128 128 kbit (16k x 8) temperature range 5 C20 c to 85 c 6 C40 c to 85 c 3 1 C40 c to 125 c operating voltage package blank 4.5 v to 5.5 v bn pdip8 (0.25 mm frame) v 2.7 v to 3.6 v mw so8 (200 mil width) w 2.5 v to 5.5 v mn 3 so8 (150 mil width) s 2 1.8 v to 3.6 v dl 4 tssop14 (169 mil width) ordering information the notation used for the device number is as shown in table 13. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office.
m95256, m95128 16/21 pdip8 C 8 pin plastic dip, 0.25mm lead frame note: 1. drawing is not to scale. pdip-8 a2 a1 a l be d e1 8 1 c ea b2 eb e pdip8 C 8 pin plastic dip, 0.25mm lead frame symb. mm inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 C C 0.100 C C ea 7.62 C C 0.300 C C eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150
17/21 m95256, m95128 so8 narrow C 8 lead plastic small outline, 150 mils body width note: drawing is not to scale. so-a e n cp b e a d c l a1 a 1 h h x 45? so8 narrow C 8 lead plastic small outline, 150 mils body width symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 C C 0.050 C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004
m95256, m95128 18/21 so8 wide C 8 lead plastic small outline, 200 mils body width note: drawing is not to scale. so-b e n cp b e a2 d c l a1 a h a 1 so8 wide C 8 lead plastic small outline, 200 mils body width symb. mm inches typ. min. max. typ. min. max. a 2.03 0.080 a1 0.10 0.25 0.004 0.010 a2 1.78 0.070 b 0.35 0.45 0.014 0.018 c 0.20 C C 0.008 C C d 5.15 5.35 0.203 0.211 e 5.20 5.40 0.205 0.213 e 1.27 C C 0.050 C C h 7.70 8.10 0.303 0.319 l 0.50 0.80 0.020 0.031 a 0 10 0 10 n8 8 cp 0.10 0.004
19/21 m95256, m95128 tssop14 - 14 lead thin shrink small outline note: 1. drawing is not to scale. tssop14-m 1 14 cp c l e e1 d a2 a a e b 7 8 a1 l1 tssop14 - 14 lead thin shrink small outline symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 5.000 4.900 5.100 0.1969 0.1929 0.2008 e 0.650 C C 0.0256 C C e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.500 0.750 0.0236 0.0197 0.0295 l1 1.000 0.0394 a 0 8 0 8
m95256, m95128 20/21 table 14. revision history date rev. description of revision 17-nov-1999 2.1 new -v voltage range added (including the tables for dc characteristics, ac characteristics, and ordering information). 07-feb-2000 2.2 new -v voltage range extended to m95256 (including ac characteristics, and ordering information). 22-feb-2000 2.3 tclch and tchcl, for the m95xxx-v, changed from 1 m s to 100ns 15-mar-2000 2.4 -v voltage range changed to 2.7-3.6v 29-jan-2001 2.5 lead soldering temperature in the absolute maximum ratings table amended illustrations and package mechanical data updated 12-jun-2001 2.6 correction to header of table 12b tssop14 illustrations and package mechanical data updated document promoted from preliminary data to full data sheet
21/21 m95256, m95128 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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